Processor Technology Seminar Presented by Intel and CISL

By Brian Bevirt
05/14/2012 - 12:00am
Participants at 8 May Intel workshop
FRCRC and Intel participants at a morning overview session in the Main Seminar Room of NCAR's Mesa Lab. —Photo by Brian Bevirt, CISL

CISL, in collaboration with Intel Corporation, organized and hosted an in-depth, one-day training seminar held at the NCAR Mesa Laboratory in Boulder, Colorado on 8 May 2012. This event was provided for staff and students of the Front Range Consortium for Research Computing (FRCRC), a group of universities and government labs located along the eastern edge of the U.S. Rocky Mountains. Seventy-five representatives participated from all of the FRCRC institutions: Colorado School of Mines, Colorado State University, NCAR, National Renewable Energy Laboratory, National Oceanic and Atmospheric Administration, University of Colorado Boulder, University of Colorado Denver, and University of Wyoming. This was the inaugural event of the Front Range Many-Core Developers Forum, which is affiliated with the FRCRC and is devoted to the goal of advancing the effective use of many-core technologies on scientific applications through training, seminars, and access to shared resources.

The seminar introduced participants to Intel’s current and future computing technologies being installed at the NCAR-Wyoming Supercomputing Center and other high-performance computing centers. Participants were briefed on Intel processor architectures – including their Xeon and Many Integrated Core (MIC) platforms – and the Intel product roadmap. Following the overviews, in-depth talks detailed programming paradigms and code optimization strategies for both Xeon and MIC platforms. Intel presenters included Mark West, Greg Anderson, James Reinders, and Ron Green.

Intel staff and presenters with Rich Loft, CISLIntel staff and presenters, from left: Darrell Black, Ron Green, Mark West, Greg Anderson, and James Reinders. At right is CISL host Rich Loft. —Photo by Brian Bevirt, CISL

Many-core processing is a key technology intended to propel high-end computing from the petascale level (1015 floating point operations per second – FLOPS – for applications using up to 100,000 processing elements or cores) to the exascale level (1018 FLOPS for applications using up to 100,000,000 cores). The milestone of exascale computing is expected to be achieved by the end of this decade. Intel’s MIC platform is a next-generation architecture designed to meet this challenge while being more versatile for running geoscience codes than architectures based on graphics processing units (GPUs). MIC technology is also designed to simplify the users’ task of porting their applications to the new systems.