CISL Work In Progress (WIP)

01/15/2014 - 9:30am to 10:30am
ML - MSR

For the CISL WIP Seminar in January we have the following speakers:

Robert Kloefkorn (IMAGe), "Aspects of Dynamical Core Development - Communication and Time Stepping"

Srinath Vadlamani (TDD), "Performance and correctness of CESM on TACC's Stampede Xeon Phis"

Pete Siemsen (OSD), "IPv6 at UCAR"

Wednesday, January 15th, 2014
Time: 9:30am
Mesa Lab Main Seminar Room

We look forward to seeing everyone there in the ML Main Seminar Room!

About WIP Seminars:

For those not familiar with the WIP Seminars, each seminar consists of 2-3 presentations, with one speaker from each of OSD, IMAGe, and TDD. Each speaker is limited to 10 minutes (and 10 slides) to present their work. The presentation should be accessible to everyone in CISL and not overly formal. Talks can address a work in progress, or anything that would be interest to other people in CISL. (These talks need NOT be completed and polished work!