CISL Seminar Series - Dr. Zakhar Matveev

03/03/2016 - 9:30am
ML-Main Seminar Room

Unlock next generation hardware performance secrets for your HPC codes; enable SIMD vector parallelism using performance analysis tools

Zakhar A. Matveev

Intel Software and Services Group

(To access the recorded session please visit

Software must be optimized for both threaded and SIMD vector parallelism to achieve scaled performance on modern hardware. The gap (> 2 orders of magnitude) between unoptimized baseline and SIMD+thread parallel code performance is increasing every year. SIMD code modernization is not without cost, but exciting new features of OpenMP 4.x “explicit vectorization” and the new Intel® “Vectorization Advisor” software tool make it possible to introduce efficient and portable SIMD parallelism without disrupting ongoing development. This seminar will also briefly cover the next generation Xeon Phi (code named Knights Landing) and AVX-512 instruction set architecture.


Zakhar A. Matveev, PhD, is a Parallel Studio product architect in the Intel Software and Services Group. His current focus is SIMD vector parallelism assistance tools. His professional interests are in the areas of high performance computing, parallel programming, computer graphics, code modernization, software design and usability.


After the seminar, Dr. Matveev will be available in the Chapman room for a more in-depth follow up conversation from 10:30-12:00. Then from 1:00-4:00, he will host a hands-on "bring your own code" session (also in the Chapman room). All are welcome. Contact John Dennis with any questions about these after-seminar sessions.

Thursday, March 3 at 9:30am

Location: NCAR Mesa Laboratory, Main Seminar Room